Recently, there is an increasing need for a high speed, high precision, and low consumption analog-to-digital conversion circuit (hereinafter called an ADC). One of proposed means for implementing a high speed and high precision ADC is an interleaved ADC in which a plurality of high precision ADCs are provided in parallel for time-dividing operation among them. Each of parallel, high precision ADCs is called a “component ADC”. As a component ADC, a pipelined ADC is usually used because it has a relatively simple configuration but provides high precision.
When a capacitor of low capacitance value is used in a pipelined ADC to meet the low power dissipation requirement, a non-linear error (INL: integral non-linearity) is caused primarily by a gain error in each pipeline stage. Therefore, to improve the INL, the gain error in each pipeline stage must be corrected. For the correction of pipelined ADC errors, refer to Non-Patent Documents 1 and 2 and Patent Document 1. Non-Patent Document 1 describes the configuration of a pipelined ADC that employs the 1.5-bit/stage algorithm. This document also describes a calibration method for a pipelined ADC offset and a gain error.
FIG. 5 is a diagram showing an example of the configuration of a correction circuit which uses a known calibration signal in order to correct a gain error. FIG. 5 shows a two-phase interleaved ADC where two component ADCs are provided in parallel. Referring to FIG. 5, in this AD conversion system includes a first AD converter 10 (also called a first component ADC) which comprises a first pipelined AD converter 11 (also called a first pipelined ADC) and a first gain error correction circuit 12; a second AD converter 20 (also called a second component ADC) which comprises a second pipelined AD converter 21 (also called a second pipelined ADC) and a second gain error correction circuit 22; a correction circuit 30A which comprises a parallel-to-serial (PS) conversion circuit (2:1 multiplexer) 31, a calibration signal replica generation unit 35, a subtracter 36, and a correction circuit control unit 34A; a calibration signal generation unit 40A; and a divide-by-2 multi-phase circuit 50.
A known calibration signal (for example, known linear ramp waveform) generated by the calibration signal generation unit 40A is sampled by the two component ADCs 10 and 20 with respective phases spaced one half period each other.
The divide-by-2 multi-phase circuit 50 divides the reference clock signal by two and generates two divided clock signals that are spaced by one half clock period each other.
The first and second pipelined ADCs 11 and 21 sample received signals with respective phases, based on the divided clock signals which are supplied from the divide-by-2 multi-phase circuit 50 and which are spaced by one half clock period each other.
In response to the output from the first and second pipelined AD converters 11 and 21, the first and second gain error correction circuits 12 and 22 correct a gain error and output the correction result (digital signal).
The parallel-to-serial conversion circuit (multiplexer) 31 receives the digital signals which are output respectively from the two component ADCs 10 and 20 that sample the calibration signal using the divided clock signals spaced by one half clock period each other, multiplexes the digital signals at the ratio of 2:1, and outputs the multiplexed signal.
The subtracter 36 outputs the difference (result of subtraction) between the digital output signal from the parallel-to-serial conversion circuit (multiplexer) 31 and the calibration signal replica (digital signal with the known linear ramp waveform) from the calibration signal replica generation unit 35.
The correction circuit control unit 34A receives the difference output from the subtracter 36, generates correction amount control signals #1 and #2 used to control the gain error correction used in the first and second gain error correction circuits 12 and 22 so that the absolute value of the difference is reduced (minimized), and supplies the generated correction amount control signals #1 and #2 to the first and second gain error correction circuits 12 and 22.
The correction circuit with the configuration described above corrects the gain error in the first and second pipelined ADCs 11 and 21 to improve the characteristics of non-linear errors caused by gain errors.
FIG. 6 is a diagram showing an example of a correction circuit with the configuration in which a low-speed and high-precision reference ADC is used for a correction method that is different from that shown in FIG. 5. Referring to FIG. 6, this conventional AD conversion system comprises a reference ADC 60, which comprises a low-speed/high-precision AD converter 61 (reference ADC), instead of the calibration signal replica generation unit 35 in FIG. 5; and a calibration signal generation unit 40B (which generates any calibration signal) instead of the calibration signal generation unit 40A (which generates a known calibration signal) in FIG. 5. The calibration signal from the calibration signal generation unit 40B is supplied to the first and second pipelined AD converters 11 and 21 and to the low-speed/high-precision reference ADC 61. Divide-by-2 multi-phase clock signals, which are output from a frequency-division multi-phase circuit 50B and are spaced each other, are supplied to the ADCs 10 and 20 respectively, and a low-speed clock signal with a divider ratio higher than that for the ADCs 10 and 20 is supplied from the frequency-division multi-phase circuit 50B to the low-speed/high-precision reference ADC 61.
That is, in the configuration shown in FIG. 6, the subtracter 36 calculates the difference between the received signal (digital signal) sampled by the ADCs 10 and 20 instead of the calibration signal replica signal in FIG. 5 and the received signal (digital signal) sampled by the low-speed/high-precision reference ADC 61. A correction circuit control unit 34B controls the correction of a gain error so that the absolute value of this difference is reduced (minimized).
While a known calibration signal is used in the configuration shown in FIG. 5, any calibration signal from the calibration signal generation unit 40B can be used in the configuration shown in FIG. 6. The calibration signal doesn't have to be a known signal as in FIG. 5. Nor is it required for the subtracter 36 to calculate the difference on every sample. Therefore, the low-speed clock signal, whose frequency is divided by the frequency-division multi-phase circuit 50B, is used for the low-speed/high-precision reference ADC 61. For an example of the configuration shown in FIG. 6, see Patent Publication 1.
[Non-Patent Document 1]
Masanori Furuta, Shoji Kawahito, and Daisuke Miyazaki, “A Digital Calibration Technique for Pipelined Analog-to-Digital Converters,” IEEE Instrumentation and Measurement Technology Conference 21–23 May 2002, pp. 713–717
[Non-Patent Document 2]
X. Wang, P. J. Hurst, and S. H. Lewis, “A 12-bit 20-MS/s Pipelined ADC with Nested Digital Background Calibration,” IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2003, pp. 409–412
[Patent Document 1]
U.S. Pat. No. 6,606,042 Specification